按键消抖：（延时20ms后输出有效值）
30S倒计时：（复位结束或开始按键按下后计时器从30开始倒计时，有选手抢答时，倒计时停止，并且输出O_cnt_flag（此信号拉高其他选手抢答无效））
工程仿真：如下图所示：
I_key代表三位选手（001（1），010（2），100（4））
I_begin高电平代表主持人按下开始按键
O_cnt_flag高电平代表有选手抢答或30S内无人抢答
I_plus,I_sub代表主持人加分和减分
I_people1,2,3代表三位选手编号输出（数码管显示）
O_score1,2,3代表三位选手分数输出（数码管显示）初始每人为10分
第一轮抢答：全局复位（I_rst）结束后，主持人按下开始按键，此时倒计时开始；选手1在倒计时为8秒时按下抢答键，此时倒计时停止，倒计时显示8直至开始按键按下，显示选手1编号（I_people1高电平）直至开始按键按下，O_cnt_flag信号拉高直至开始按键按下；选手2慢于选手1按下抢答键，抢答无效，不显示选手2编号，选手1答对问题后主持人加一分（11分），显示分数（O_score1）。
第二轮抢答：主持人按下开始键，此时倒计时从30开始倒计时，选手1在倒计时15时按下抢答键，
............选手1又答对了，再加一分（12）分。
第三轮抢答：主持人按下开始键，此时倒计时从30开始倒计时，选手2在倒计时12时按下抢答键,..............选手2打错，扣一分（9）分
第四轮抢答：主持人按下开始键，无人抢答，倒计时结束后O_cnt_flag拉高，选手4抢答，抢答无效。
复位键按下，分数全部归10，比赛结束。
按键消抖：
`timescale 1ns / 1ps//// Company: // Engineer: // // Create Date: /12/08 14:41:34// Design Name: // Module Name: delete_dou// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //module delete_dou(//自锁式按键input I_clk, //外部 50M 时钟input I_rst, //外部复位信号，低有效input I_key, //外部按键输入 按键按下为低电平output reg O_key_value //按键消抖后的数据 );reg [31:0] S_delay_cnt; reg S_key_reg; //***************************************************** //** main code //***************************************************** always @(posedge I_clk) begin if (I_rst) begin S_key_reg <= 1'b0; end else begin S_key_reg <= I_key; endendalways @(posedge I_clk) begin if (I_rst) begin S_delay_cnt <= 32'd0; // end else if(S_key_reg ^ I_key)begin //一旦检测到按键状态发生变化(有按键被按下或释放) end else if((S_key_reg == 1)&&(S_key_reg ^ I_key))begin //检测上升沿S_delay_cnt <= 32'd100; //给延时计数器重新装载初始值（计数时间为 20ms(上板时1000_1000),板子仿真时20us（1000）） end else if((S_key_reg == 1)&&(S_delay_cnt > 32'd0))begin S_delay_cnt <= S_delay_cnt - 1'b1;end else beginS_delay_cnt <= S_delay_cnt;end end always @(posedge I_clk) beginif (I_rst) beginO_key_value <= 3'b0; end else if(S_delay_cnt == 32'd1) begin //当计数器递减到 1 时，说明按键稳定状态维持了 20msO_key_value <= 1; //并寄存此时按键的值end else beginO_key_value <= 1'd0;end endendmodule
计时模块：
`timescale 1ns / 1ps//// Company: // Engineer: // // Create Date: /12/08 15:10:48// Design Name: // Module Name: cnt_x// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //module cnt_x(input I_clk ,input I_rst ,input I_begin,input [2:0] I_key ,output regO_cnt_flag ,//表明30S倒计时结束或有人抢答output reg [4:0] O_cnt // output [3:0] O_data_ge ,// output [3:0] O_data_shi);reg [25:0] S_cnt;wire I_rst_n;assign I_rst_n = !I_rst;//S_cntalways @(posedge I_clk) begin if (!I_rst_n||I_begin || (S_cnt == 26'd34_999)) begin S_cnt <= 26'd0; end else if((I_key == 0)&&(O_cnt_flag == 0)) begin//有人按下按键S_cnt <= S_cnt+1;end else begin S_cnt <= S_cnt; endend//O_cntalways @(posedge I_clk) begin if (!I_rst_n||I_begin) begin O_cnt <= 5'd30; end else if(S_cnt == 26'd34_999) begin//有人按下按键O_cnt <= O_cnt-1;end else begin O_cnt <= O_cnt; endendalways @(posedge I_clk) begin if (!I_rst_n||I_begin) begin O_cnt_flag <= 1'b0; end else if(O_cnt == 5'd0 || (I_key != 0)) begin O_cnt_flag <= 1; end else beginO_cnt_flag <= O_cnt_flag; endend// assign O_data_ge = S_cnt % 4'd10; // 个位数// assign O_data_shi = S_cnt / 4'd10 % 4'd10 ; // 十位数endmodule
抢答模块：
`timescale 1ns / 1ps//// Company: // Engineer: // // Create Date: /12/08 15:26:41// Design Name: // Module Name: ctrl_people// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //module ctrl_people(input I_clk ,//1Minput I_rst , input I_cnt_flag ,input [2:0] I_key , input I_begin,output regO_people1 ,output regO_people2 ,output regO_people3); always @(posedge I_clk) begin if (I_rst||I_begin) begin O_people1 <= 1'd0; end else if((I_cnt_flag == 0)&&I_key[0])begin O_people1 <= 1'd1; end else beginO_people1 <= O_people1; endendalways @(posedge I_clk) begin if (I_rst||I_begin) begin O_people2 <= 1'd0; end else if((I_cnt_flag == 0)&&I_key[1])begin O_people2 <= 1'd1; end else beginO_people2 <= O_people2; endend always @(posedge I_clk) begin if (I_rst||I_begin) begin O_people3 <= 1'd0;end else if((I_cnt_flag == 0)&&I_key[2])begin O_people3 <= 1'd1; end else beginO_people3 <= O_people3; endend endmodule
得分模块：
`timescale 1ns / 1ps//// Company: // Engineer: // // Create Date: /12/08 15:55:50// Design Name: // Module Name: score// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //module score(input I_clk ,//1Minput I_rst , input I_begin,input I_people1 ,input I_people2 ,input I_people3 ,input I_plus,input I_sub,output reg [3:0]O_score1 , output reg [3:0]O_score2 , output reg [3:0]O_score3 );// reg S_plus;// reg S_sub;//always @(posedge I_clk) begin // if (I_rst||I_begin) begin // S_plus <= 1'd0; // S_sub <= 1'd0; // end else begin// S_plus <= I_plus; // S_sub <= I_sub; // end//end// reg plus_up;// reg sub_up;//always @(posedge I_clk) begin // if (I_rst||I_begin) begin // plus_up <= 1'd0;// end else if(S_plus^I_plus)begin// plus_up <= plus_up + 1;// end else begin// plus_up <= plus_up;// end//end//always @(posedge I_clk) begin // if (I_rst||I_begin) begin // sub_up <= 1'd0;// end else if(S_sub^I_sub)begin// sub_up <= sub_up + 1;// end else begin// sub_up <= sub_up;// end//endalways @(posedge I_clk) begin if (I_rst) begin O_score1 <= 4'd10; end else if(I_people1&&(I_plus == 1))begin O_score1 <= O_score1 + 1; end else if(I_people1&&(I_sub == 1))begin O_score1 <= O_score1 - 1; end else beginO_score1 <= O_score1;endendalways @(posedge I_clk) begin if (I_rst) begin O_score2 <= 4'd10; end else if(I_people2&&(I_plus == 1))begin O_score2 <= O_score2 + 1; end else if(I_people2&&(I_sub == 1))begin O_score2 <= O_score2 - 1; end else beginO_score2 <= O_score2;endend always @(posedge I_clk) begin if (I_rst) begin O_score3 <= 4'd10; end else if(I_people3&&(I_plus == 1))begin O_score3 <= O_score3 + 1; end else if(I_people3&&(I_sub == 1))begin O_score3 <= O_score3 - 1; end else beginO_score3 <= O_score3;endend endmodule
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